`timescale 1ns / 1ps
module io_test(CLK_I, READ_I, WRITE_I, ADDR_I, DATA_I, DATA_O);
    input CLK_I;
    input READ_I;
    input WRITE_I;
    input [31:0] ADDR_I;
    input [15:0] DATA_I;
    
    output [15:0] DATA_O;
   
    	
	`define IO_BASE_ADDR 32'h0B000000

reg [15:0] memory;

wire select;

assign select = (`IO_BASE_ADDR == ADDR_I);

always @(posedge CLK_I)
begin
	if (WRITE_I && select)
	begin
		memory <= DATA_I;
	end
end

assign DATA_O = (READ_I && select) ? memory : 16'h0;

endmodule
